Tharas Systems Delivers 4-state Hardware-Assisted Verification Solution

Tharas Systems, Inc., a leading provider of high-performance, hardware-assisted verification solutions, today announced its support for Verilog 4-state logic simulation in Hammer 100. Delivering the EDA industry's only hardware accelerator with 4-state support, Hammer 100 can now detect and propagate 4-valued logic - "0", "1", "X" and "Z" similar to a Verilog software simulator. This significantly shrinks the "Time-to-Performance" while enhancing overall verification accuracy.

Traditionally engineers have utilized the 4-state capability of the Verilog simulation language to pessimistically model design elements. This capability helps uncover issues associated with reset logic, random initialization, bus conflicts, un-initialized registers and ATPG-based verification. In the past, since hardware-assisted verification tools only supported 2-state logic ("0" and "1"), engineers had to simplify 4-state dependent models to match software simulation results especially in the test bench. This can be a laborious process and can result in a potential loss of accuracy in certain situations. Hammer 100 now uniquely offers functionality similar to a software simulator. The 4-valued accelerated simulation capability is backward compatible with Hammer 100 hardware.

"Our goal is to bring complex SoC designs to market on schedule, without compromising verification accuracy. Toshiba recognizes the vital need for 4-valued simulation capability in a hardware accelerator to achieve faster design migration from the software simulation environment. We worked closely with Tharas to implement such a feature in Hammer 100 Accelerator," notes Mr. Seiichi Nishio, senior manager, System LSI Design Division of Toshiba Corporation Semiconductor Company. "With this capability now in place, Toshiba looks forward to deploy a practical verification methodology using Hammer and delivery of other enhancements to address RTL and gate-level sign-off requirements."

"With 4-state support, Tharas offers the most accurate hardware-assisted verification solution in the industry," says Rahm Shastry, president and CEO of Tharas Systems. "Migrating designs from simulation to hardware-assisted tools often requires remodeling ASIC cells such as pads, memories, and tri-state-based logic. This break through capability eliminates re-modeling of such cells or re-writing of 4-state dependent initialization sequences. We are delighted that Toshiba partnered with us to implement this ground-breaking capability in Hammer 100."

Pricing and Product Availability

The Hammer 4-state capable compiler option is available for production use immediately on Solaris and Linux-based platforms. It is an add-on option to Hammer compiler, version 4.0. List price for a perpetual license of this option is US $20,000. It is also available through T-FORCE, Tharas' Flexible On-demand Rental Collaborative Environment program. For more information, call Tharas Systems in North America at 408.855.3200. For pricing and availability outside of North America visit http://www.tharas.com/contact for appropriate contact information.

Product Demonstration

The 4-state support is integrated with the latest release of the Hammer Compiler, version 4.0, which will be demonstrated at the Electronic Design and Solution Fair in Yokohama, Japan, Exhibit Booth #111, January 27-28 and DVCon in Santa Clara, California, Exhibit Booth #403, February 14-15, 2005.

Contacts

Tharas Systems, Inc.
Sanjay Sawant, 408-855-3207
sanjay@tharas.com
or
VitalCom Marketing & PR
Karen Tyrrell, 650-366-8212 x204
karen@vitalcompr.com